@Vlad00n memory timings are subjective depending on if you are aiming for highest possible frequency with lowest possible timings or simply running stock frequency with tight timings. If you want the latter start with a TRRD of 5 or 6 and IMC between 0.9v - 0.96v. If you want the latter start with a TRRD of 7 (8 is only really needed when pushing for 2300MHz+ but efficiency starts taking a hit at this point). Any 580/590 card I tested I generally settled on 2200MHz as that was always the optimal speed to efficiency barrier but not all memory is going to be able to hit 2200MHz it’s a pretty hard slog getting a card stable at that speed, 2150MHz is much easier and if you are looking for maximum speed at lowest possible voltage for power efficiency then definitely aim for 2150MHz as the IMC should be perfectly happy running that speed on 0.85v-0.9v.
@ket I’m not aiming for higher clocks, 2150-2175 is the max that I want. At this point I have 1411 Mhz Core with 1085mv, and memory with the strap that I thanked you about with 2150 and 960mv on the Mem controller. Don’t want to push more voltages to the memory, neither to the core, these settings are good for me. I would like to keep the card cool and efficient as you said. If you have any suggestions for a bit better timings, I would happily test them. And this will be my final tuning of this card 
Hello @ket.
For 1 month now I’m using this strap : 777000000000000022EE9C00106A7D4DA06914153C8EC60B004684007D0714204A8900A00200712414143F48BC324C1A with 945mv on the IMC, 2150Mhz mem clock, and core clock of 1411MHz at 1085mv. With these settings I got only 1 memory error once, so I decided that I could live with that. But today I got a lot of artefacting.
I red your comment about the ras timings that they could still be relaxed, but probably my memory could not handle that. Could you please give me and advice what can I change to fix the issue.
####SEQ_WR_CTL_D1####
DAT_DLY = 7
DQS_DLY = 7
DQS_XTR = 0
DAT_2Y_DLY = 0
ADR_2Y_DLY = 0
CMD_2Y_DLY = 0
OEN_DLY = 7
OEN_EXT = 0
OEN_SEL = 0
ODT_DLY = 0
ODT_EXT = 0
ADR_DLY = 0
CMD_DLY = 0
####SEQ_WR_CTL_2####
DAT_DLY_H_D0 = 0
DQS_DLY_H_D0 = 0
OEN_DLY_H_D0 = 0
DAT_DLY_H_D1 = 0
DQS_DLY_H_D1 = 0
OEN_DLY_H_D1 = 0
WCDR_EN = 0
####SEQ_PMG_TIMING####
TCKSRE = 2
TCKSRX = 2
TCKE_PULSE = 14
TCKE = 14
SEQ_IDLE = 7
TCKE_PULSE_MSB = 1
SEQ_IDLE_SS = 0
####SEQ_RAS_TIMING####
TRCDW = 16=>?
TRCDWA = 16=>?
TRCDR = 26=>?
TRCDRA = 26=>?
TRRD = 7
TRC = 77
####SEQ_CAS_TIMING####
TNOPW = 0
TNOPR = 0
TR2W = 26=>27
TCCDL = 4
TCCDS = 6
TW2R = 20
TCL = 21
####SEQ_MISC_TIMING####
TRP_WRA = 60
TRP_RDA = 28
TRP = 26
TRFC = 188
####SEQ_MISC_TIMING2####
PA2RDATA = 0
PA2WDATA = 0
TFAW = 6=>7
TCRCRL = 2
TCRCWL = 4
T32AW = 4
TWDATATR = 0
####ARB_DRAM_TIMING####
ACTRD = 20=>22
ACTWR = 20=>22
RASMACTRD = 63
RASMACTWR = 72
####ARB_DRAM_TIMING2####
RAS2RAS = 188
RP = 50
WRPLUSRP = 76
BUS_TURN = 26
####MC_SEQ_MISC####
MC_SEQ_MISC1 = 0x2014077D
MC_SEQ_MISC3 = 0xA000894A
MC_SEQ_MISC8 = 0x24710002
Please tell me your opinion.
Thank you in advance.
TR2W 28, TRP_WRA 62, TRP_RDA 29, TFAW 4, RP 56. Once you verify that’s stable you can try stepping down TRP_RDA to 28.