I managed to extract the PE32 file from the BIOS and found the parts that supposedly contain the CFG lock and undervolt protection, the manual voltage offset for the p-cores. When I write with setup_var, I get the error: error: can’t set variable using efi (error: 0x8000000000000008)
I tried to make the change using Ru.EFI and got the same error 0x00000008.
Will I have to use a BIOS reader and flash it with a burner?
How does the BIOS write lock manifest itself? If I remove the locks, I’ll want to customize it completely.
Summary
0xA08CF One Of: Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR , VarStoreInfo (VarOffset/VarName): 0x49, VarStore: 0x2, QuestionId: 0x1E3, Size: 1, Min: 0x0, Max 0x7, Step: 0x0 {05 91 B0 06 B1 06 E3 01 02 00 49 00 10 10 00 07 00}
0xA08E0 One Of Option: When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset), Value (8 bit): 0x0 (default) {09 07 B2 06 30 00 00}
0xA08E7 One Of Option: CFG Lock, Value (8 bit): 0x1 {09 07 B3 06 00 00 01}
0xA08EE One Of Option: Configure MSR 0xE2[15], CFG Lock bit, Value (8 bit): 0x2 {09 07 B4 06 00 00 02}
0xA08F5 One Of Option: Interrupt Redirection Mode Selection, Value (8 bit): 0x7 {09 07 B5 06 00 00 07}
0xA08FC End One Of {29 02}
0xA08FE Suppress If {0A 82}
0xA0900 QuestionId: 0x1293 equals value 0x0 {12 06 93 12 00 00}
0xA674C Numeric: When UnderVolt Protection is enabled, user will not be able to program under voltage in OS runtime. Recommended to keep it enabled by default. Enabled: Allow BIOS undervolting, but enable UnderVolt Protection in Runtime. Disabled: No UnderVolt Protection in Runtime., VarStoreInfo (VarOffset/VarName): 0x236, VarStore: 0x2, QuestionId: 0x3D4, Size: 2, Min: 0x0, Max 0x3E8, Step: 0x1 {07 94 87 1D C6 1C D4 03 02 00 36 02 10 11 00 00 E8 03 01 00}
0xA6760 Default: DefaultId: 0x0, Value (16 bit): 0x0 {5B 07 00 00 01 00 00}
0xA6767 End {29 02}
0xA6F55 Numeric: UnderVolt Protection, VarStoreInfo (VarOffset/VarName): 0x27E, VarStore: 0x2, QuestionId: 0x405, Size: 2, Min: 0x0, Max 0x3E8, Step: 0x1 {07 94 86 1D C5 1C 05 04 02 00 7E 02 10 11 00 00 E8 03 01 00}
0xA6F69 Default: DefaultId: 0x0, Value (16 bit): 0x0 {5B 07 00 00 01 00 00}
0xA6F70 End {29 02}
0xA63E9 Numeric: Specifies the Offset Voltage applied to the Global Performance-core domain. This voltage is specified in millivolts. Uses Mailbox MSR 0x150, cmd 0x11. Range -500 to 500 mV, VarStoreInfo (VarOffset/VarName): 0x266, VarStore: 0x2, QuestionId: 0x3BE, Size: 2, Min: 0x0, Max 0x3E8, Step: 0x1 {07 94 B9 1C BA 1C BE 03 02 00 66 02 10 11 00 00 E8 03 01 00}
0xA63FD Default: DefaultId: 0x0, Value (16 bit): 0x0 {5B 07 00 00 01 00 00}
0xA6404 End {29 02}