I purchased an obscure NAS only sold to the Chinese domestic market (Zspace Z4Pro) with a view to using another OS on it since it was intel based (i3-N305)
For reasons unknown the power to the drive bays is individually controlled with an npn + mosfet driven by a GPIO.
The default state is off and then toggled from within the stock OS - possibly as a rudimentary measure to prevent using another OS or possibly (given the SMBIOS is full of “Default Strings”) they just didn’t know what they were doing.
GPIOs
| gpio_name | gpio_number | pad_name | DW0 | DW1 | DW2 |
|---|---|---|---|---|---|
| sata0_power_gpio | 681 | GPPC_B_17 | 0x04000201 | 0x00000029 | 0x00000100 |
| sata1_power_gpio | 680 | GPPC_B_16 | 0x04000201 | 0x00000028 | 0x00000100 |
| sata2_power_gpio | 672 | GPPC_B_8 | 0x04000201 | 0x00000020 | 0x00000100 |
| sata3_power_gpio | 671 | GPPC_B_7 | 0x04000201 | 0x0000001f | 0x00000100 |
DW0 Register (0x04000201)
| Bit Range | Field Name | Description | Value |
|---|---|---|---|
| 31-30 | PADRSTCFG | Pad Reset Config | 0x0 (Powergood) |
| 29-29 | RXPADSTSEL | RX Pad State Select | 0x0 (Raw RX pad state directly from CFIO RX buffer) |
| 28-28 | RXRAW1 | RX Raw Override to ‘1’ | 0x0 (No Override) |
| 27-27 | NAF_VWE | Native Function Virtual Wire Message Enable | 0x0 (Disable pad input event sampling and VW message generation.) |
| 26-25 | RXEVCFG | RX Level/Edge Configuration | 0x2 (Disable) |
| 24-24 | PREGFRXSEL | Pre Glitch Filter Stage RX Pad State Select | 0x0 (Select synchronized, non filtered RX pad state) |
| 23-23 | RXINV | RX Invert | 0x0 (No inversion) |
| 22-21 | RXTXENCFG | RX/TX Enable Config | 0x0 (Function defined in Pad Mode controls TX and RX Enables) |
| 20-20 | GPIROUTIOXAPIC | GPIO Input Route IOxAPIC | 0x0 (Routing does not cause peripheral IRQ) |
| 19-19 | GPIROUTSCI | GPIO Input Route SCI | 0x0 (Routing does not cause SCI) |
| 18-18 | GPIROUTSMI | GPIO Input Route SMI | 0x0 (Routing does not cause SMI) |
| 17-17 | GPIROUTNMI | GPIO Input Route NMI | 0x0 (Routing does not cause NMI) |
| 16-13 | RESERVED | Reserved | 0x0 |
| 12-10 | PMODE | Pad Mode | 0x0 (GPIO controls the Pad) |
| 9-9 | GPIORXDIS | GPIO RX Disable | 0x1 (Disable the input buffer of the pad) |
| 8-8 | GPIOTXDIS | GPIO TX Disable | 0x0 (Enable the output buffer (active low enable) of the pad) |
| 7-2 | RESERVED | Reserved | 0x0 |
| 1-1 | GPIORXSTATE | GPIO RX State | 0x0 (Current internal RX pad state is 0) |
| 0-0 | GPIOTXSTATE | GPIO TX State | 0x1 (Drive a level ‘1’ to the TX output pad) |
I’m struggling to understand where the DW0 registers are set; I’d like to modify GPIOTXSTATE for each of those 4 pads to drive 0, not 1.
These are not set by DSDT.
Any pointers very much appreciated.
Download:
z4pro_bios_T7310X02.bin