[REQUEST] GA-H77-D3H (rev. 1.1) Unlocking frequency ratios for i5-3570K

Now before anything else, I’m aware that a H77 motherboard isn’t meant for full OC like a Z77, so let’s skip that discussion, the reason I’m asking for this, is because my BIOS allows for full control over all the meaningful voltages for an OC (check my screenshots), but then Gigabyte remembered this is a H77 mo-bo and decided to gray out the Turbo frequency ratios and limited the CPU clock ratio to 36, but they allowed base clock OC, which is riskier than CPU clock OC, it makes no sense!?

All of that makes me wonder if those frequency ratios can’t be unlocked by a BIOS mod, especially that I have an i5-3570K and I’m more than certain this motherboard is capable of handling a 40.0 ratio at the least, can it be done?

Thanks in advance for your time.
Direct link to latest stock BIOS from Gigabyte, which I’m using but with updated ME and uCodes: F16b

Bumping this in case the right people missed it.

I have the same question just post here to get replied. It did find out it’s because of MSR_PLATFORM_INFO bit 28 not being set to 1 (enabled)

x86_64 Overclocking · Issue #67 · cyring/CoreFreq (github.com)

(UEFI) Dell XPS 15z L511z modded BIOS - and HOWTO (bios-mods.com)

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Believe me when I say I’ve spent the last 8 hours digging through the internet to find how to enable bit 28, found nothing of value, either I’m bad at searching, reading, both, or Google is losing its magic.
And searching for it using IDA returns some results but I have no experience with Assembly nor IDA, this feels so close, yet so far.
I found this and did exactly what was suggested there, but I don’t think I even needed to mess with MSR 0x194 since I already have an i5-3570K.


I also found this and reading MSR 0xCE gave me this, that 0x22 means a ratio of 34.


Then MSR 0x1AD gave me this, 0x24 means a 36 ratio, 0x25 = 37 and 0x26 = 38.


I don’t know how to proceed from here.
So unfortunate Lost_N_BIOS has disappeared.

Any more help would be appreciated.

There’s no ratio value being set by MSR_PLATFORM_INFO.

You need to try patching MSR 0xCE bit 28 from reporting 01 to remove ratio limit.
0xE0012200 to 0xE0002200. E.g. in your BIOS there MAY BE a piece of code sending 10000h to 0xCE on every boot.

Nah. We actually need to get bit 28 to 1. Right?


mov esi, 0xCE

or eax, 1000000h


Thank you for giving this a try.
This is what I’m seeing when I open powermanagement.pe using IDA and searching for 0xCE

How can I patch it?
I’m really new to IDA, so please go slow.

That’s not it.

Keywords are: bts (“bit test and set” operand), or (stores the register value in the destination location), wrmsr (this one can be in a different subroutine).
0xCE value is likely following the “mov” operand.

I think this is it because I’m seeing 0x1AD and a bt operand (bit test maybe!?), that’s the limit of my monkey brain with the limited knowledge I have at the moment.

I’ve just noticed your edit.
There are 5 occurences of 0xCE and they’re all like this:
mov ecx, 0CEh

I haven’t gotten very far on this either. Do not think that the solution will be that simple only because I have something to add.
Atm I’m struggling making out how registers work and going further and further I understand what the hell I was writing before.

Could you show all of them?

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EDIT: enough guessing, here’s a peace of code with additions.

//MSR1(1) bit is set
//MSR1(0) bit is not set

		{ 63, 4, "NOT DOCUMENTED BITS (probably can allow MSR_OC_MAILBOX)", "R/O", PRESENT_DEC, {
		// Skip 12 bits, proceed from the 60th.
		{ 59, 12, RESERVED },
		{ 47, 8, "Maximum Efficiency Ratio", "R/O", PRESENT_DEC, {
		{ 39, 8, "Core Voltage", "R/O", PRESENT_DEC, {
			// MSR_PERF_STATUS[37:32] * (float) 1/(2^13)
		{ 31, 1, "Number of ConfigTDP Levels", "R/O", PRESENT_BIN, {
			{ MSR1(0), "Additional TDP level(s) not available" },
			{ MSR1(1), "Additional TDP level(s) available" },
		{ 30, 1, "Low Power Mode Support/Programmable TJ Offset", "R/O", PRESENT_BIN, {
			{ MSR1(0), "not supported" },
			{ MSR1(1), "supported" },
		{ 29, 1, "Programmable TDC-TDP Limit for Turbo Mode", "R/O", PRESENT_BIN, {
			{ MSR1(0), "TDC and TDP Limits for Turbo Mode are not programmable" },
			{ MSR1(1), "TDC and TDP Limits for Turbo Mode are programmable" },
		{ 28, 1, "Programmable Ratio Limit for Turbo Mode of MSR_TURBO_RATIO_LIMIT 0X1AD", "R/O", PRESENT_BIN, {
			{ MSR1(0), "Programmable Ratio Limit for Turbo Mode is R/O" },
		// Skip 5 bits, proceed from the 27th.
		{ 27, 5, RESERVED },
		{ 23, 1, "Programmable Ratio Limit for Turbo Mode of MSR_TURBO_RATIO_LIMIT 0X1AD", "R/O", PRESENT_BIN, {
			{ MSR1(1), "Programmable Ratio Limit for Turbo Mode is R/W" },
		// Skip 8 bits, proceed from the 23rd.
		{ 22, 7, RESERVED },
		{ 15, 8, "Maximum Non-Turbo Ratio", "R/O", PRESENT_DEC, {
			/* This is ratio of the frequency that invariant TSC runs at. The invariant
			 * TSC requency can be computed by multipying this ratio by 133.33 Mhz.
		// Skip 7 bits.
		{ 7, 7, RESERVED },


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What you wrote on the image is exactly what I attempted to do a couple minutes ago, saved everything, repacked the bios and flashed it but it didn’t work, maybe there are other limitations!
I’m quite sure my patch didn’t do what I imagined it would do, mainly because it’s 3 AM here, and my knowledge of Assembly is non-existent at the worst and rusty at best.
I’ll dig into this again in the morning, thank you for your time and effort, and if you’ve got any other tips, drop them here and I’ll check them when I wake up.
Good night.

Intel docs say it’s R/O so is it enabled on Z motherboards from ME or what ?

If bit 28 is enabled you should be able to adjust ratios with ThrottleStop

Indeed. It says that the MSR is just enumerator for features. It might be that the values to be set are coming from Intel ME.

And there is no ready-made solution. That’s frustrating.
Try editing “bt rax, 1Ch” to “bts rax, 1Ch”.
1C is 28 in decimal.
Also ensure the code will be executed.

EDIT: Forgot that it is necessary to write the new value to MSR. Blindly guessing, the subroutine with wrmsr is 180003C5C.
If so, change will be the next:
“E8 1F 1D 00 00 48 0F BA E0 1C 73 25” to
“90 0F BA E8 1C E8 1F 24 00 00 EB 00”.